`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:39:51 11/19/2020 
// Design Name: 
// Module Name:    mips 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module mips(
    input clk,
    input reset
    );
	wire regDst,jump,jumpReg,branch,memToReg,memWrite,aluSrc,regWrite,link,PC2Reg;
	wire [1:0]aluOp;
	wire [1:0]extOp;
	wire [5:0]opCode;
	wire [5:0]func;
	ctrl controller(
		.opCode(opCode),
		.func(func),
		.regDst(regDst),
		.jump(jump),
		.jumpReg(jumpReg),
		.branch(branch),
		.memToReg(memToReg),
		.aluOp(aluOp),
		.extOp(extOp),
		.memWrite(memWrite),
		.aluSrc(aluSrc),
		.regWrite(regWrite),
		.link(link),
		.PC2Reg(PC2Reg)
	);
	datapath cpuPath(
		.clk(clk),
		.reset(reset),
		.regDst(regDst),
		.jump(jump),
		.jumpReg(jumpReg),
		.branch(branch),
		.memToReg(memToReg),
		.aluOp(aluOp),
		.extOp(extOp),
		.memWrite(memWrite),
		.aluSrc(aluSrc),
		.regWrite(regWrite),
		.link(link),
		.opCode(opCode),
		.func(func),
		.PC2Reg(PC2Reg)
	);

endmodule
